A Floating-Gate Trimmed, 14-Bit, 250 Ms/s Digital-to-Analog Converter in Standard 0.25μm CMOS

We describe a floating-gate trimmed, 14-bit, 250Ms/s current-steered DAC fabricated in a 0.25μm CMOS logic process. We trim the static INL to ±0.3LSB using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm of die area, consumes 53mW at 250MHz, allows on-chip electrical trimming, and achieves 72dB SFDR at 250Ms/s. Introduction Emerging standards for communications systems require digital-to-analog converters (DAC) with sample rates in the hundreds of Ms/s, and resolutions of 10–14 bits [1]. Designers typically use current-steering DACs for these applications because they are fast and can drive output loads without buffering. However, the static linearity of a current-steering DAC is sensitive to current-source mismatch. Designers often use large devices, randomized layouts, laser trimming, or continuous on-line electrical trimming [2–4] to reduce this mismatch. These techniques improve linearity, but at the expense of die area, power dissipation, or dynamic performance. Analog-valued floating-gate MOSFETs are near-ideal current sources for a DAC, because they allow post-fabrication electrical trimming of their output current, and because they store a trim value almost indefinitely. They also allow small current-source transistors, because trimming removes matching constraints from the design equation. We have previously described floating-gate pFETs, fabricated in standard CMOS logic processes, that store analog charge on a floating gate with 16-bit resolution [5]. We have also described how to use these devices to trim a DAC current-source array [6], although the DAC described in [6] was capable of only static outputs (i.e. no dynamic performance). In this paper we describe an entirely new 14-bit DAC with ±0.3LSB INL (an order of magnitude improved over the DAC in [6]), and dynamic performance that benefits from using small transistors. DAC Architecture Fig. 1 shows the DAC architecture, and Fig. 2 a die plot. The DAC is segmented as 5 thermometer-decoded MSBs, 9 binary-decoded LSBs, and an additional LSB for trimming. The digital circuitry comprises a 14-bit input data register, a 5-to-31 thermometer decoder to set the MSB current switches, and a 41-bit register to drive the differential-pair switches for the MSB, LSB, and trim-LSB sections. The 41-bit register uses an internally regulated low-voltage supply to minimize its voltage swings (and thereby glitch energy) during differential-pair switching. The thermometer and binary current sources are arranged in a single current-source array. We optimized the transistor placement to minimize errors from both linear and quadratic bus-drop gradients. Each of the 41 current sources comprises a static (untrimmable) source and an associated floating-gate trimmable source. Each trimmable source can trim the output current over a ±5 LSB range. A current mirror in each trim cell allows us to either add the trim current to, or subtract the trim current from, the associated static source, providing a bidirectional trim capability. A digital polarity bit holds the trim state (add or subtract) for each source. The return-to-zero (RZ) switch at the array output shorts the differential output wires together during codeword switching, further reducing output glitch energy. We use the correlated-double-sampling (CDS) comparator for trimming. R e g Trim Current Sources Polarity Register Vinj Vtun Iref pdata pclk RZclk btrim b1–14